1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a decoding technique of a semiconductor memory device.
2. Description of the Related Art
In recent years, the information technology (IT) has considerably progressed, and a data processing apparatus can carry out very complex processing of a large amount of data in a very short time. In accompaniment by this, a semiconductor memory device is made to have a large scale, so that the number of bits of an address is increased. Thus, a hierarchical decoding operation is necessitated. Also, the semiconductor memory device is required to operate in a low power supply voltage for reduction of power consumption. On the other hand, an electrically rewritable non-volatile memory as a flash memory, which can store data for a long time, is often used for recording a control program of an electronic apparatus. The flash memory requires a higher voltage than a normal power supply voltage for rewriting a data. As a consequence, the flash memory internally handles a plurality of kinds of voltages of relatively high and relative low voltages. Therefore, it is necessary to balance a circuit handling the relatively high voltage and a circuit handling the relatively low voltage in the operation speed and the voltage.
In U.S. Pat. No. 6,433,583, a CMOS switch circuit of a high voltage transition type, more specifically, a decoder circuit for a non-volatile memory is disclosed. In the CMOS switch circuit, a signal on the output side is fed back to the input side, to restrict a switching current so that power consumption is reduced.